The present disclosure relates generally to the field of integrated circuit package bond pads and, more specifically, to an integrated circuit package bond pad having a plurality of conductive members.
Semiconductor device geometries continue to dramatically decrease in size since such devices were first introduced several decades ago. Today's fabrication plants are routinely producing devices having feature dimensions less than 90 nm. Of course, such scaling has been accompanied by obstacles involving implementing new processes and equipment technology especially as device requirements become more demanding.
Typical semiconductor devices include a stack of various types of films formed over a device layer, the stack substantially comprising layers of metal and/or other conductive materials and dielectric layers interposing the conductive layers. One or more bond pads are typically formed in a topmost conductive layer, followed by a packaging layer having openings exposing the bond pads. The stack of layers can suffer internal stress due, for example, to lattice mismatches at interfaces between adjacent layers. The stress may also build-up within the stack as the device is exposed to changes in the environment, the application of force and thermal cycling during manufacturing, assembly, packaging and handling. The dielectric layers typically comprise low-k materials that are sensitive to stresses that can occur during and after manufacturing and assembly. Consequently, the stress build-up in and around the dielectric layers can cause cracking and peeling of various layers, adversely affecting device performance and reliability.
One of the processes which can contribute to the stress build-up in the stack of layers is package bonding. For example, in a wire bonding process, a small-diameter wire comprising gold and/or other conductive materials is electrically and mechanically coupled to a bond pad. Generally, one or more of the application force, thermal energy and acoustic energy used in bonding the wire causes the terminus of the wire to bond with the bond pad, thereby allowing connection of the integrated circuit package with an external feature, such as a circuit board. Wire bonding and other bonding processes induce mechanical and thermal stress in and around the bond pad, including in the conductive and dielectric layers underlying the bond pad. As discussed above, the build-up of such stress can be detrimental to the performance and reliability of the integrated circuit package and, consequently, the electronic device incorporating the integrated circuit package.
Accordingly, what is needed in the art is an integrated circuit package bond pad and method of manufacture thereof that addresses the above-discussed issues of the prior art.